RISC-V from Software to Silicon: Programming, Linux, FPGA, and AI Applications Training Course

RISC-V Architecture Fundamentals and Ecosystem Overview

RISC-V ISA Landscape and Industry Adoption

• The philosophy of open ISAs and the standardization landscape maintained by RISC-V International
• Understanding the RISC-V mental model: Load-Store architecture, register files, and byte ordering
• Comparative analysis with ARM, x86, and POWER: evaluating trade-offs in heterogeneous computing
• Assessing ecosystem maturity across SiFive, T-Head, Western Digital, and the expanding open-source silicon community
• Standardized interfaces including the RISC-V Privileged ISA and the Machine Software Abstraction Layer (MSBL)

Memory Models and ABI Compliance

• Unprivileged Architecture specifications covering the CSR map, exception handling, and memory hierarchies
• RV32I and RV64I instruction sets with focus on ABI compliance for cross-platform binary portability
• Memory ordering conventions and the use of barrier instructions in multiprocessor systems

RISC-V Assembly Programming and Compiler Toolchain

Low-Level Instruction Programming

• Exploring base integer (I), Multiply/Divide (M), and Atomic operations (A) extensions
• Implementing bitness-aware programming strategies for 32-bit and 64-bit RISC-V targets
• Managing calling conventions and stack frames for embedded and real-time software systems

Compiler Toolchain Proficiency

• Utilizing the LLVM-based toolchain, including Clang, LLVM, and Binutils for RISC-V cross-compilation
• Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments
• Applying compiler intrinsics, optimization levels, and profiling-driven code tuning
• Developing open-source toolchain workflows: building, testing, and packaging custom GCC and Clang toolchains

Embedded Systems Development and Real-Time Operating Systems

Bare-Metal and RTOS Programming

• Rust systems programming for RISC-V: leveraging zero-cost abstractions, unsafe memory management, and bare-metal development
• Working in No-Std environments: custom linkers, device driver development, and memory-mapped I/O
• Developing with Zephyr RTOS and Buildroot BSP for RISC-V targets
• Peripheral interfacing techniques for GPIO, I2C, SPI, UART, and DMA controllers

Power and Performance Optimization

• Optimizing through clock gating, power domain management, and low-power modes
• Conducting cycle-accurate performance analysis using simulation profilers and hardware performance counters
• Tuning real-time interrupt latency for safety-critical applications

Linux Kernel and Bootloader Development for RISC-V

Boot Firmware and Bootloader Ecosystem

• Implementing the SBI specification via OpenSBI for bootloader firmware development
• Developing modern firmware boot stacks using UEFI/EDK II on RISC-V
• Porting Coreboot and U-Boot for RISC-V single-board computers

Linux Kernel Integration

• Contributing to the RISC-V mainline kernel: device tree overlays, CPU topology, and AIA interrupt controller drivers
• Developing vendor BSPs and configuring kernels for custom SoC platforms
• Supporting file systems, networking stacks, and containerization (Docker, Kubernetes) on RISC-V hosts

RISC-V SoC Design and FPGA Prototyping

Multicore SoC Architecture and Integration

• Designing Network-on-Chip (NoC) methodologies for RISC-V multi-core processors
• Implementing Axi4/CHI cache coherence and inter-processor communication protocols
• Integrating open-source IP from OpenCores, ChIPS Framework, and vendor RTL components
• Designing bus matrices and integrating memory controllers for DDR, SRAM, eMMC, and PCIe

FPGA-Based Processor Prototyping

• Synthesizing and implementing RISC-V cores on FPGA, such as BOOM, VexRiscv, and PULP
• Applying SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
• Utilizing formal verification tools and property-based testing for RISC-V core validation

RISC-V Vector Extensions and Domain-Specific Acceleration

RVV (RISC-V Vector) Extension Deep Dive

• Vector load/store, vector-fused multiply-add (VFMA), and matrix computation acceleration
• Variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution
• Vector mask operations, segment control, and data type flexibility for DSP and ML workloads

Custom DSP and Domain-Specific Instruction Design

• Designing domain-specific accelerators using custom extensions and CBAR-based operand interfaces
• Modifying compiler frontends for custom instruction generation and code emission
• Applying hardware-software partitioning strategies for accelerator integration in production SoCs

AI Acceleration and Edge Machine Learning on RISC-V

NPU Design and Integration for RISC-V Processors

• Neural Processing Unit architecture: systolic arrays, tensor cores, and weight compression for on-chip AI
• Model quantization techniques (INT8, INT4, FP8) for edge deployment on RISC-V
• Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets

Heterogeneous Computing for AI Workloads

• Co-designing RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines
• Optimizing memory subsystems: HBM/DDR bandwidth management for ML model weights and activations
• Managing thermal and power budgets for edge AI inference systems

Hardware Security and Confidential Computing on RISC-V

Physical Memory Protection and Trusted Execution

• Physical Memory Protection (PMP) and Page Table walker security mechanisms
• Secure Enclave and TEE architectures for RISC-V: OP-TEE integration and SEV-class trusted execution environments
• Boot chain security: establishing root of trust, secure boot, and measured launch attestation

Cryptographic Acceleration

• RISC-V cryptographic extensions (Zk, Zkr, K): accelerating SHA, AES, RSA, RSA-PSS, and ECC
• Integrating post-quantum cryptography (PQC) for next-generation RISC-V processors
• Mitigating side-channel attacks via constant-time programming, masking, and hardware random number generators

Advanced Custom Architecture and ISA Extension Design

Domain-Specific Architecture and Custom Instruction Extensions

• ISA extension design methodology: encoding, tables, ABI impact analysis, and RISC-V International submission processes
• Custom register file design using CBAR (Custom Base Address Registers) for operand dispatch
• Instruction pipelining, hazard detection, and pipeline modifications for custom extensions

Verification and Signoff of Custom Architecture Modifications

• Testbench design for custom extensions: directed vs. constraint-random stimulus generation
• Regression testing frameworks and coverage-driven verification for architectural changes
• Interoperability testing: ensuring custom instructions function within established ABI constraints

Safety-Critical and Automotive RISC-V Applications

Functional Safety and Automotive Standards Compliance

• ISO 26262 functional safety compliance for RISC-V automotive processors
• ASIL-Q classification and safety manual development for RISC-V silicon IP
• Deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical systems

Industrial Real-Time and Edge Computing Applications

• IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
• Developing Industrial IoT gateways with RISC-V: connectivity, edge analytics, and OTA firmware updates

Capstone Project: End-to-End RISC-V System Development

Full Lifecycle Project

• Architecture specification: designing ISA extensions and core configurations for a defined use case
• RTL implementation in SystemVerilog with UVM testbenches and formal verification coverage
• FPGA prototyping, boot firmware development, and bare-metal driver stack integration
• Linux BSP and toolchain customization for the custom RISC-V core
• AI workload deployment: NPU integration, model quantization, and performance benchmarking
• Security validation: PMP enforcement, secure boot, and cryptographic acceleration benchmarking
• Technical architecture documentation, IP strategy analysis, and cross-functional team presentation